diff --git a/multi-ram.ld b/multi-ram.ld
index e3c16ca..41872f1 100644
--- a/multi-ram.ld
+++ b/multi-ram.ld
@@ -7,9 +7,9 @@
  */
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */
-  RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K */
-  RAM2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8K */
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K */
+  RAM (rwx) : ORIGIN = 0x1FFFFC00, LENGTH = 0x400 /* 1K */
+  RAM2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0xC00 /* 3K */
 }
 
 /* Linker script to place sections and symbol values. Should be used together
diff --git a/startup_ARMCM0.s b/startup_ARMCM0.s
index 4a9f5fb..7358e9e 100644
--- a/startup_ARMCM0.s
+++ b/startup_ARMCM0.s
@@ -30,6 +30,11 @@
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
+
+/* CHANGING DEFINES */
+#define __STARTUP_COPY_MULTIPLE
+#define __STARTUP_CLEAR_BSS_MULTIPLE
+
 	.syntax	unified
 	.arch	armv6-m
 
diff --git a/sysinit.c b/sysinit.c
new file mode 100644
index 0000000..4d3f406
--- /dev/null
+++ b/sysinit.c
@@ -0,0 +1,32 @@
+#include "MKL05Z4.h"
+
+#define MCG_C4_DC0_25PMAX_MID (MCG_C4_DMX32_MASK | (1 << MCG_C4_DRST_DRS_SHIFT))
+
+// comments here are pretty poor since I barly understand what's going on
+void SystemInit() 
+{
+    __asm("cpsid i");
+
+    SIM_COPC = 0; // disable COP watchdog timer
+
+    /***** set 48-MHz clock, 24-MHz bus clock ******/
+
+    SIM_SCGC5 |= 0x00000200; // port A mask
+    PORTA_PCR3 = PORT_PCR_ISF_MASK;
+    PORTA_PCR4 = PORT_PCR_ISF_MASK;
+    SIM_CLKDIV1 = 1 << SIM_CLKDIV1_OUTDIV4_SHIFT; // changes clock divider
+    MCG_C2 = MCG_C2_EREFS0_MASK; // osc settings
+    OSC0_CR = OSC_CR_ERCLKEN_MASK; // external ref clock
+    MCG_C1 = MCG_C1_IRCLKEN_MASK;
+
+    while (MCG_S & MCG_S_OSCINIT0_MASK); // wait for osc to become stable
+    while (!(MCG_S & MCG_S_IREFST_MASK)); // wait for FLL and external clock to match
+
+    // preserve FCTRIM and SCFTRIM
+    MCG_C4 = ((MCG_C4 & -MCG_C4_DRST_DRS_MASK) | MCG_C4_DC0_25PMAX_MID);
+
+    // wait for output of FLL to be selected
+    while (!(MCG_S & MCG_S_CLKST_MASK));
+
+    /****************************/
+}