diff --git a/main.c b/main.c
index e977dff..a59c915 100644
--- a/main.c
+++ b/main.c
@@ -23,27 +23,27 @@
 // *********************************************
 
 void Init_LEDs (void) {
-  /* Enable clock for PORT B module */
-  SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
+	/* Enable clock for PORT B module */
+	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
 
-  /* Select PORT B Pin 8 for GPIO to red LED */
-  PORTB_PCR(POS_RED) = PORT_PCR_SET_GPIO;
-  /* Select PORT B Pin 9 for GPIO to green LED */
-  PORTB_PCR(POS_GREEN) = PORT_PCR_SET_GPIO;
-  /* Select PORT B Pin 10 for GPIO to blue LED */
-  PORTB_PCR(POS_BLUE) = PORT_PCR_SET_GPIO;
+	/* Select PORT B Pin 8 for GPIO to red LED */
+	PORTB_PCR(POS_RED) = PORT_PCR_SET_GPIO;
+	/* Select PORT B Pin 9 for GPIO to green LED */
+	PORTB_PCR(POS_GREEN) = PORT_PCR_SET_GPIO;
+	/* Select PORT B Pin 10 for GPIO to blue LED */
+	PORTB_PCR(POS_BLUE) = PORT_PCR_SET_GPIO;
 
-  // FGPIOB_PDDR = PORTB_LEDS_MASK;
-  FGPIOB_PCOR = PORTB_LED_BLUE_MASK;
-  FGPIOB_PSOR = PORTB_LED_GREEN_MASK;
-  FGPIOB_PSOR = PORTB_LED_RED_MASK;
-  
-  /* Turn off LEDs */
-  // FGPIOB_PSOR = PORTB_LEDS_MASK;
+	// FGPIOB_PDDR = PORTB_LEDS_MASK;
+	FGPIOB_PCOR = PORTB_LED_BLUE_MASK;
+	FGPIOB_PSOR = PORTB_LED_GREEN_MASK;
+	FGPIOB_PSOR = PORTB_LED_RED_MASK;
+
+	/* Turn off LEDs */
+	// FGPIOB_PSOR = PORTB_LEDS_MASK;
 }
 
 void main()
 {
-  Init_LEDs();
-  for (;;);
+	Init_LEDs();
+	for (;;);
 }
diff --git a/sysinit.c b/sysinit.c
index 68e4f08..12174d8 100644
--- a/sysinit.c
+++ b/sysinit.c
@@ -5,28 +5,28 @@
 // comments here are pretty poor since I barely understand what's going on
 void SystemInit() 
 {
-  __asm("cpsid i");
+	__asm("cpsid i");
 
-  SIM_COPC = 0; // disable COP watchdog timer
+	SIM_COPC = 0; // disable COP watchdog timer
 
-  /***** set 48-MHz clock, 24-MHz bus clock ******/
+	/***** set 48-MHz clock, 24-MHz bus clock ******/
 
-  SIM_SCGC5 |= 0x00000200; // port A mask
-  PORTA_PCR3 = PORT_PCR_ISF_MASK;
-  PORTA_PCR4 = PORT_PCR_ISF_MASK;
-  SIM_CLKDIV1 = 1 << SIM_CLKDIV1_OUTDIV4_SHIFT; // changes clock divider
-  MCG_C2 = MCG_C2_EREFS0_MASK; // osc settings
-  OSC0_CR = OSC_CR_ERCLKEN_MASK; // external ref clock
-  MCG_C1 = MCG_C1_IRCLKEN_MASK;
+	SIM_SCGC5 |= 0x00000200; // port A mask
+	PORTA_PCR3 = PORT_PCR_ISF_MASK;
+	PORTA_PCR4 = PORT_PCR_ISF_MASK;
+	SIM_CLKDIV1 = 1 << SIM_CLKDIV1_OUTDIV4_SHIFT; // changes clock divider
+	MCG_C2 = MCG_C2_EREFS0_MASK; // osc settings
+	OSC0_CR = OSC_CR_ERCLKEN_MASK; // external ref clock
+	MCG_C1 = MCG_C1_IRCLKEN_MASK;
 
-  while (!(MCG_S & MCG_S_OSCINIT0_MASK)); // wait for osc to become stable
-  while (MCG_S & MCG_S_IREFST_MASK); // wait for FLL and external clock to match
+	while (!(MCG_S & MCG_S_OSCINIT0_MASK)); // wait for osc to become stable
+	while (MCG_S & MCG_S_IREFST_MASK); // wait for FLL and external clock to match
 
-  // preserve FCTRIM and SCFTRIM
-  MCG_C4 = ((MCG_C4 & -MCG_C4_DRST_DRS_MASK) | MCG_C4_DC0_25PMAX_MID);
+	// preserve FCTRIM and SCFTRIM
+	MCG_C4 = ((MCG_C4 & -MCG_C4_DRST_DRS_MASK) | MCG_C4_DC0_25PMAX_MID);
 
-  // wait for output of FLL to be selected
-  while (MCG_S & MCG_S_CLKST_MASK);
+	// wait for output of FLL to be selected
+	while (MCG_S & MCG_S_CLKST_MASK);
 
-  /****************************/
+	/****************************/
 }