fixed make process
This commit is contained in:
parent
66c466f699
commit
900ca67858
8
Makefile
8
Makefile
|
@ -1,8 +1,10 @@
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CC=arm-none-eabi-gcc
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ARCH_FLAGS=-mthumb -mcpu=cortex-m0plus
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CFLAGS=$(ARCH_FLAGS) -Os -flto -ffunction-sections -fdata-sections -D__STARTUP_COPY_MULTIPLE -D__STARTUP_CLEAR_BSS_MULTIPLE
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CFLAGS=$(ARCH_FLAGS) -Os -flto -ffunction-sections -fdata-sections
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USE_NANO=--specs=nano.specs
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USE_NOHOST=--specs=nosys.specs
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STARTUP_DEFS=-D__STARTUP_COPY_MULTIPLE -D__STARTUP_CLEAR_BSS_MULTIPLE -D__START=main
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SPECS=--specs=nano.specs --specs=nosys.specs
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# Link for code size
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GC=-Wl,--gc-sections
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@ -12,8 +14,8 @@ MAP=-Wl,-Map=main.map
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LDSCRIPTS=-L. -T multi-ram.ld
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main.axf: main.c sysinit.c startup_ARMCM0.s
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$(CC) $^ $(CFLAGS) -fno-exceptions $(USE_NANO) $(USE_NOHOST) $(LDSCRIPTS) $(GC) $(MAP) -o $@
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main.axf: main.c sysinit.c startup_ARMCM0.S
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$(CC) $^ $(CFLAGS) -fno-exceptions $(SPECS) $(STARTUP_DEFS) $(LDSCRIPTS) $(GC) $(MAP) -o $@
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clean:
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rm -f *.axf *.map
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263
startup_ARMCM0.S
Normal file
263
startup_ARMCM0.S
Normal file
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@ -0,0 +1,263 @@
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/* File: startup_ARMCM0.S
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* Purpose: startup file for Cortex-M0 devices. Should use with
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* GCC for ARM Embedded Processors
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* Version: V2.0
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* Date: 16 August 2013
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*
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* Copyright (c) 2011 - 2013 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
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||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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.syntax unified
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.arch armv6-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0xc00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .isr_vector
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long Default_Handler
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.size __isr_vector, . - __isr_vector
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.text
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.thumb
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.thumb_func
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.align 1
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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#ifdef __STARTUP_COPY_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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blt .L_loop0_0_done
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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b .L_loop0_0
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.L_loop0_0_done:
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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#else
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .L_loop1_done
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.L_loop1:
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subs r3, #4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .L_loop1
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.L_loop1_done:
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#endif /*__STARTUP_COPY_MULTIPLE */
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* There are two schemes too. One can clear multiple BSS sections. Another
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* can only clear one section. The former is more size expensive than the
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* latter.
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*
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* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
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*/
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#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of tuples specifying:
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* offset 0: Start of a BSS section
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* offset 4: Size of this BSS section. Must be multiply of 4
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*/
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ldr r3, =__zero_table_start__
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ldr r4, =__zero_table_end__
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.L_loop2:
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cmp r3, r4
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bge .L_loop2_done
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ldr r1, [r3]
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ldr r2, [r3, #4]
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movs r0, 0
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.L_loop2_0:
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subs r2, #4
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blt .L_loop2_0_done
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str r0, [r1, r2]
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b .L_loop2_0
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.L_loop2_0_done:
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adds r3, #8
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b .L_loop2
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.L_loop2_done:
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#elif defined (__STARTUP_CLEAR_BSS)
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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subs r2, r1
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ble .L_loop3_done
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.L_loop3:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop3
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.L_loop3_done:
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#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
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#ifndef __NO_SYSTEM_INIT
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bl SystemInit
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#endif
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#ifndef __START
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#define __START _start
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#endif
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bl __START
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler DEF_IRQHandler
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.end
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217
startup_ARMCM0.s
217
startup_ARMCM0.s
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@ -1,45 +1,18 @@
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/* File: startup_ARMCM0.S
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* Purpose: startup file for Cortex-M0 devices. Should use with
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* GCC for ARM Embedded Processors
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||||
* Version: V2.0
|
||||
* Date: 16 August 2013
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||||
*
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* Copyright (c) 2011 - 2013 ARM LIMITED
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||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
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# 0 "startup_ARMCM0.S"
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# 0 "<built-in>"
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# 0 "<command-line>"
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# 1 "startup_ARMCM0.S"
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# 33 "startup_ARMCM0.S"
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.syntax unified
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.arch armv6-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
|
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#else
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|
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.equ Stack_Size, 0xc00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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|
@ -50,11 +23,11 @@ __StackTop:
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|
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.section .heap
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.align 3
|
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#ifdef __HEAP_SIZE
|
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.equ Heap_Size, __HEAP_SIZE
|
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#else
|
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|
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|
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|
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.equ Heap_Size, 0
|
||||
#endif
|
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|
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.globl __HeapBase
|
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.globl __HeapLimit
|
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__HeapBase:
|
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|
@ -69,24 +42,24 @@ __HeapLimit:
|
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.align 2
|
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.globl __isr_vector
|
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__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
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.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
.long __StackTop
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long SVC_Handler
|
||||
.long 0
|
||||
.long 0
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_Handler
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
@ -98,55 +71,7 @@ __isr_vector:
|
|||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
blt .L_loop0_0_done
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
b .L_loop0_0
|
||||
|
||||
.L_loop0_0_done:
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
# 150 "startup_ARMCM0.S"
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
@ -161,77 +86,13 @@ Reset_Handler:
|
|||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
blt .L_loop2_0_done
|
||||
str r0, [r1, r2]
|
||||
b .L_loop2_0
|
||||
.L_loop2_0_done:
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
# 229 "startup_ARMCM0.S"
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
bl _start
|
||||
|
||||
.pool
|
||||
|
@ -245,9 +106,9 @@ Default_Handler:
|
|||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
|
||||
|
||||
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
|
|
Loading…
Reference in a new issue