added system init and edited linker file
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@ -7,9 +7,9 @@
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*/
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */
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RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K */
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RAM2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8K */
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FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K */
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RAM (rwx) : ORIGIN = 0x1FFFFC00, LENGTH = 0x400 /* 1K */
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RAM2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0xC00 /* 3K */
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}
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/* Linker script to place sections and symbol values. Should be used together
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@ -30,6 +30,11 @@
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/* CHANGING DEFINES */
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#define __STARTUP_COPY_MULTIPLE
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#define __STARTUP_CLEAR_BSS_MULTIPLE
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.syntax unified
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.arch armv6-m
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32
sysinit.c
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32
sysinit.c
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@ -0,0 +1,32 @@
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#include "MKL05Z4.h"
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#define MCG_C4_DC0_25PMAX_MID (MCG_C4_DMX32_MASK | (1 << MCG_C4_DRST_DRS_SHIFT))
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// comments here are pretty poor since I barly understand what's going on
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void SystemInit()
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{
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__asm("cpsid i");
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SIM_COPC = 0; // disable COP watchdog timer
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/***** set 48-MHz clock, 24-MHz bus clock ******/
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SIM_SCGC5 |= 0x00000200; // port A mask
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PORTA_PCR3 = PORT_PCR_ISF_MASK;
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PORTA_PCR4 = PORT_PCR_ISF_MASK;
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SIM_CLKDIV1 = 1 << SIM_CLKDIV1_OUTDIV4_SHIFT; // changes clock divider
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MCG_C2 = MCG_C2_EREFS0_MASK; // osc settings
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OSC0_CR = OSC_CR_ERCLKEN_MASK; // external ref clock
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MCG_C1 = MCG_C1_IRCLKEN_MASK;
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while (MCG_S & MCG_S_OSCINIT0_MASK); // wait for osc to become stable
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while (!(MCG_S & MCG_S_IREFST_MASK)); // wait for FLL and external clock to match
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// preserve FCTRIM and SCFTRIM
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MCG_C4 = ((MCG_C4 & -MCG_C4_DRST_DRS_MASK) | MCG_C4_DC0_25PMAX_MID);
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// wait for output of FLL to be selected
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while (!(MCG_S & MCG_S_CLKST_MASK));
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/****************************/
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}
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