fixed indentation
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34
main.c
34
main.c
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@ -23,27 +23,27 @@
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// *********************************************
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void Init_LEDs (void) {
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/* Enable clock for PORT B module */
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SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
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/* Enable clock for PORT B module */
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SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
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/* Select PORT B Pin 8 for GPIO to red LED */
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PORTB_PCR(POS_RED) = PORT_PCR_SET_GPIO;
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/* Select PORT B Pin 9 for GPIO to green LED */
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PORTB_PCR(POS_GREEN) = PORT_PCR_SET_GPIO;
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/* Select PORT B Pin 10 for GPIO to blue LED */
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PORTB_PCR(POS_BLUE) = PORT_PCR_SET_GPIO;
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/* Select PORT B Pin 8 for GPIO to red LED */
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PORTB_PCR(POS_RED) = PORT_PCR_SET_GPIO;
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/* Select PORT B Pin 9 for GPIO to green LED */
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PORTB_PCR(POS_GREEN) = PORT_PCR_SET_GPIO;
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/* Select PORT B Pin 10 for GPIO to blue LED */
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PORTB_PCR(POS_BLUE) = PORT_PCR_SET_GPIO;
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// FGPIOB_PDDR = PORTB_LEDS_MASK;
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FGPIOB_PCOR = PORTB_LED_BLUE_MASK;
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FGPIOB_PSOR = PORTB_LED_GREEN_MASK;
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FGPIOB_PSOR = PORTB_LED_RED_MASK;
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/* Turn off LEDs */
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// FGPIOB_PSOR = PORTB_LEDS_MASK;
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// FGPIOB_PDDR = PORTB_LEDS_MASK;
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FGPIOB_PCOR = PORTB_LED_BLUE_MASK;
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FGPIOB_PSOR = PORTB_LED_GREEN_MASK;
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FGPIOB_PSOR = PORTB_LED_RED_MASK;
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/* Turn off LEDs */
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// FGPIOB_PSOR = PORTB_LEDS_MASK;
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}
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void main()
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{
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Init_LEDs();
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for (;;);
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Init_LEDs();
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for (;;);
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}
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34
sysinit.c
34
sysinit.c
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@ -5,28 +5,28 @@
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// comments here are pretty poor since I barely understand what's going on
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void SystemInit()
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{
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__asm("cpsid i");
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__asm("cpsid i");
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SIM_COPC = 0; // disable COP watchdog timer
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SIM_COPC = 0; // disable COP watchdog timer
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/***** set 48-MHz clock, 24-MHz bus clock ******/
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/***** set 48-MHz clock, 24-MHz bus clock ******/
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SIM_SCGC5 |= 0x00000200; // port A mask
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PORTA_PCR3 = PORT_PCR_ISF_MASK;
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PORTA_PCR4 = PORT_PCR_ISF_MASK;
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SIM_CLKDIV1 = 1 << SIM_CLKDIV1_OUTDIV4_SHIFT; // changes clock divider
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MCG_C2 = MCG_C2_EREFS0_MASK; // osc settings
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OSC0_CR = OSC_CR_ERCLKEN_MASK; // external ref clock
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MCG_C1 = MCG_C1_IRCLKEN_MASK;
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SIM_SCGC5 |= 0x00000200; // port A mask
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PORTA_PCR3 = PORT_PCR_ISF_MASK;
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PORTA_PCR4 = PORT_PCR_ISF_MASK;
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SIM_CLKDIV1 = 1 << SIM_CLKDIV1_OUTDIV4_SHIFT; // changes clock divider
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MCG_C2 = MCG_C2_EREFS0_MASK; // osc settings
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OSC0_CR = OSC_CR_ERCLKEN_MASK; // external ref clock
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MCG_C1 = MCG_C1_IRCLKEN_MASK;
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while (!(MCG_S & MCG_S_OSCINIT0_MASK)); // wait for osc to become stable
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while (MCG_S & MCG_S_IREFST_MASK); // wait for FLL and external clock to match
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while (!(MCG_S & MCG_S_OSCINIT0_MASK)); // wait for osc to become stable
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while (MCG_S & MCG_S_IREFST_MASK); // wait for FLL and external clock to match
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// preserve FCTRIM and SCFTRIM
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MCG_C4 = ((MCG_C4 & -MCG_C4_DRST_DRS_MASK) | MCG_C4_DC0_25PMAX_MID);
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// preserve FCTRIM and SCFTRIM
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MCG_C4 = ((MCG_C4 & -MCG_C4_DRST_DRS_MASK) | MCG_C4_DC0_25PMAX_MID);
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// wait for output of FLL to be selected
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while (MCG_S & MCG_S_CLKST_MASK);
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// wait for output of FLL to be selected
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while (MCG_S & MCG_S_CLKST_MASK);
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/****************************/
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/****************************/
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}
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